Airbender’s execution model uses RISC-V 32I+M and a fetch-decode-execute loop, processing bytecode in approximately 4 million-cycle chunks with horizontal scaling and Kernel Mode for system-level operations.

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Airbender implements the RISC-V 32I+M instruction set, operating in a standard fetch-decode-execute loop. Bytecode is loaded via ROM and processed in chunks of ~4 million cycles. Prover performance can be scaled horizontally by stitching chunks together via memory arguments. The system supports Kernel Mode for ZKsync OS system-level logic.