Architecture & execution model

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Airbender’s execution model uses RISC-V 32I+M and a fetch-decode-execute loop, processing bytecode in approximately 4 million-cycle chunks with horizontal scaling and Kernel Mode for system-level operations.

Airbender achieves high throughput on a single GPU using a five-stage proving pipeline, which includes: witness commitment, memory validation, constraint encoding, DEEP polynomial construction and FRI-based proximity proof generation

Airbender is built on AIR constraints compiled into DEEP STARK proofs over a Mersenne31 field, supporting recursive proving and precompiled circuits, while maintaining compatibility with EVM, EraVM and WASM through ZKsync OS

Airbender supports hybrid CPU/GPU proving, RAM-backed registers, and CSRRW-based custom precompiles, enabling optimized cryptographic operations and big integer arithmetic

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